The present invention relates to integrated circuits having protrusions in a substrate. Examples of such integrated circuits include floating gate memories with substrate protrusions.
FIG. 1A is a perspective view of a conventional NAND memory with floating gates 102. FIG. 1B shows a vertical cross section of the memory along a plane DD′ shown in FIG. 1A. Plane DD′ passes through channel regions 104 and source/drain regions 106. Floating gates 102 are conductive elements made from doped polysilicon. Substrate isolation regions 108 (“field oxide” or FOX) are formed in P-type silicon substrate 110. Silicon dioxide 120 (“tunnel oxide”) is formed on substrate 110 under the floating gates. ONO 130 (a sandwich of silicon oxide, silicon nitride, silicon oxide) insulates the floating gates from word lines (WL) 134. The word lines provide control gates used to control the floating gate voltages.
P-type channel regions 104 are portions of substrate 110 under the floating gates 102. Each channel region 104 is flanked by N-type source/drain regions 106 formed in substrate 110 on opposite sides of each floating gate 102. Each source/drain region 106 is shared by two adjacent memory cells in a string of memory cells connected in series, except for the source/drain regions 106 at the ends of the string.
The floating gates are programmed and erased via electron transfer between the floating gates and the substrate 110. The memory is read by sensing the current through a memory cell. NAND memory operation is described, for example, in U.S. Pat. No. 6,262,926 issued Jul. 17, 2001 to Nakai and incorporated herein by reference. See also U.S. Pat. No. 6,714,447 issued Mar. 30, 2004 to Satoh et al. and incorporated herein by reference.
In order to successfully scale the memory to low voltage operation, the current drive of the memory cells should be increased because the increased current would facilitate fast determination of the state of the cell. The current drive can be increased by reducing the thickness of tunnel oxide 120, but then data retention would be compromised as the charge leakage from the floating gates would increase. The current drive can also be increased by enlarging the memory cells, but this is also undesirable as smaller memories are in demand.
Therefore, there is a need for alternative memory structures and integrated circuit fabrication methods. There also seems to be always a demand for new fabrication methods capable to provide smaller features with a given photolithographic technology.